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JEDEC JESD47K

STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS

Pages: 34
Publication date: 2018-08-01
Price: 76 vnd

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This standard describes a baseline set of acceptance tests for use in qualifying electronic components as new products, a product family, or as products in a process which is being changed.
Document identifier
JEDEC JESD47K
Title
STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS
JEDEC Category
JC-14.3: Silicon Devices Reliability Qualification and Monitoring
Publication date
2018-08-01
Status
Effective
International Relationship
Cross references
Latest version
JEDEC JESD47K
STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS
Document identifier JEDEC JESD47K
Publication date 2018-08-01
Classification
Status Effective
*
History of version
JEDEC JESD47K * JEDEC JESD47J.01 * JEDEC JESD47J * JEDEC JESD47I.01 * JEDEC JESD47I * JEDEC JESD47H * JEDEC JESD 47G.01
Keywords
Classification
Pages
34
Price 76 vnd

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