The HBM DRAM is tightly coupled to the host compute die with a distributed interface. The interface is
divided into independent channels. Each channel is completely independent of one another. Channels are
not necessarily synchronous to each other. The HBM DRAM uses a wide-interface architecture to achieve
high-speed, low power operation. Each channel interface maintains a 128 bit data bus operating at double
data rate (DDR).
Document identifier
JEDEC JESD235B
Title
HIgh Bandwidth Memory DRAM (HBM1, HBM2)
JEDEC Category
JC-42.4: Non-Volatile Memory Devices
Publication date
2018-11-01
International Relationship
History of version
JEDEC JESD235B * JEDEC JESD235A * JEDEC JESD235
| Price |
228 vnd |
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