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JEDEC JEP156A

CHIP-PACKAGE INTERACTION UNDERSTANDING, IDENTIFICATION AND EVALUATION

Pages: 24
Publication date: 2018-03-01
Price: 67 vnd

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This publication references a set of frequently recommended and accepted JEDEC reliability stress tests. These tests are used for qualifying new and modified technology/ process/ product families, as well as individual solid state surface-mount products.
Document identifier
JEDEC JEP156A
Title
CHIP-PACKAGE INTERACTION UNDERSTANDING, IDENTIFICATION AND EVALUATION
JEDEC Category
JC-14.3: Silicon Devices Reliability Qualification and Monitoring
Publication date
2018-03-01
Status
Effective
International Relationship
Cross references
Latest version
JEDEC JEP156A
CHIP-PACKAGE INTERACTION UNDERSTANDING, IDENTIFICATION AND EVALUATION
Document identifier JEDEC JEP156A
Publication date 2018-03-01
Classification
Status Effective
*
History of version
JEDEC JEP156A * JEDEC JEP156
Keywords
Classification
Pages
24
Price 67 vnd

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