The HBM DRAM is tightly coupled to the host compute die with a distributed interface. The interface is divided into independent channels. Each channel is completely independent of one another. Channels are not necessarily synchronous to each other. The HBM DRAM uses a wide-interface architecture to achieve high-speed, low-power operation. The HBM DRAM uses differential clock CK_t/CK_c. Commands are registered at the rising edge of CK_t, CK_c. Each channel interface maintains a 28b data bus operating at DDR data rates.
Document identifier
JEDEC JESD235
Title
HIGH BANDWIDTH MEMORY (HBM) DRAM
JEDEC Category
JC-42.4: Non-Volatile Memory Devices
Publication date
2013-10-01
International Relationship
History of version
JEDEC JESD235B*JEDEC JESD235 * JEDEC JESD235B * JEDEC JESD235A * JEDEC JESD235
| Price |
191 vnd |
JEDEC JESD235
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