This stress test is intended to determine the ability of an EEPROM integrated circuit or an integrated circuit with an EEPROM module (such as a microprocessor) to sustain repeated data changes without failure (program/erase endurance) and to retain data for the expected life of the EEPROM (data retention). This Standard specifies the procedural requirements for performing valid endurance and retention tests based on a qualification specification. Endurance and retention qualification specifications (for cycle counts, durations, temperatures, and sample sizes) are specified in JESD47 or may be developed using knowledge-based methods as in JESD94.
Document identifier
JEDEC JESD22-A117E
Title
ELECTRICALLY ERASABLE PROGRAMMABLE ROM (EEPROM) PROGRAM/ERASE ENDURANCE AND DATA RETENTION TEST
JEDEC Category
JC-14.3: Silicon Devices Reliability Qualification and Monitoring
Publication date
2018-11-01
International Relationship
History of version
JEDEC JESD22-A117E * JEDEC JESD22-A117D * JEDEC JESD22-A117C * JEDEC JESD 22-A117B
| Price |
67 vnd |
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