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IEC 62530 Ed. 2.0 en:2011

SystemVerilog - Unified Hardware Design, Specification, and Verification Language

Pages: 1251
Publication date: 2011-05-19
Price: 410 vnd

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IEC 62530:2011(E) Provides a unified Hardware Design, Specification, and Verification language. IEEE Std 1364TM-2005 Verilog is a design language. Both standards were approved by the IEEE-SASB in November 2005. This standard creates new revisions of the IEEE 1364 Verilog and IEEE 1800 SystemVerilog standards, which include errata fixes and resolutions, enhancements, enhanced assertion language, merger of Verilog Language Reference Manual (LRM) and SystemVerilog 1800 LRM into a single LRM, integration with Verilog-AMS, and ensures interoperability with other languages such as SystemC and VHDL. This publication has the status of a double logo IEEE/IEC standard.
Document identifier
IEC 62530 Ed. 2.0 en:2011
Title
SystemVerilog - Unified Hardware Design, Specification, and Verification Language
IEC Category
TC 91: Electronics assembly technology, TC 93: Design automation
Publication date
2011-05-19
Status
Effective
International Relationship
Cross references
Latest version
IEC 62530 Ed. 2.0 en:2011
SystemVerilog - Unified Hardware Design, Specification, and Verification Language
Document identifier IEC 62530 Ed. 2.0 en:2011
Publication date 2011-05-19
Classification 25.040. Industrial automation systems
25.040.01. Industrial automation systems in general
Status Effective
*
History of version
IEC 62530 Ed. 2.0 en:2011 * IEC 62530 Ed. 1.0 en:2007
Keywords
Classification
25.040. Industrial automation systems
25.040.01. Industrial automation systems in general
Pages
1251
Price 410 vnd

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