As ball grid array component pitch continues to decrease, the need to characterize solder voiding
has become more significant. Solder void manifestation (type and/or sizes) has been used to
determine process capability as a means of quality assurance during process transfer, and as
indicators of process stability from in-line manufacturing monitors. This document describes
how to characterize voids in solder spheres in ball grid array packages prior to surface-mount
(SMT) reflow soldering.
Document identifier
JEDEC JESD217.01
Title
TEST METHODS TO CHARACTERIZE VOIDING IN PRE-SMT BALL GRID ARRAY PACKAGES
JEDEC Category
JC-14: Quality and Reliability of Solid State Products
Publication date
2016-10-01
International Relationship
History of version
JEDEC JESD217.01 * JEDEC JESD217
| Price |
87 vnd |
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