JEDEC JESD252 is intended for use by SoC, ASIC, ASSP, and FPGA developers or vendors interested in incorporating a signaling protocol for hardware resetting the Serial Flash device. In is also intended for use by peripheral developers or vendors interested in providing Serial Flash devices compliant with the standard. This standard defines a signaling protocol that allows the host to reset the slaved Serial Flash device without a dedicated hardware reset pin.
Document identifier
JEDEC JESD252
Title
SERIAL FLASH RESET SIGNALING PROTOCOL
JEDEC Category
JC-14.3: Silicon Devices Reliability Qualification and Monitoring
Publication date
2018-10-01
International Relationship
| Price |
53 vnd |
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