New IEEE Standard - Inactive-Withdrawn.
Withdrawn Standard. Withdrawn Date: Mar 06, 2000. No longer endorsed by the IEEE. Recommendations are provided for the layout and test methods required to characterize properly latchup behavior in CMOS and BiCMOS integrated circuit processes or other processes that have similar lateral PNPN topographical layout characteristics. The aim is to allow the characterization of an integrated circuit process architecture so that different approaches can be scientifically compared. This allows the evaluation of the process capabilities on a worst-case recommended structure and test method independent of an actual integrated circuit product topographical latchup layout practices. Test structures and test philosophy are covered.
Document identifier
IEEE 1181-1991
Title
IEEE Recommended Practice for Latchup Test Methods for CMOS and BiCMOS Integrated- Circuit Process Characterization
IEEE Category
Electron Devices
Publication date
1991-12-13
International Relationship
| Price |
178 vnd |
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