This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTUB32865 registered buffer with parity for 2 rank by 4 or similar high-density DDR2 RDIMM applications. The SSTUB32865 is identical in functionality to the SSTU32865 but specifies tighter timing characteristics and a higher application frequency of up to 410MHz.
Document identifier
JEDEC JESD 82-24
Title
DEFINITION OF the SSTUB32865 28-bit 1:2 REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS
JEDEC Category
JC-40: Digital Logic
Publication date
2007-05-01
International Relationship
| Price |
72 vnd |
.jpg){kind=logo}
---Logo.jpg){kind=logo}
.jpg){kind=logo}
-_-logo.png){kind=logo}
.jpg){kind=logo}
.png)
