This document describes an algorithm for performing the Standard Wafer Level Electromigration Accelerated Test (SWEAT) method with computer controlled instrumentation. The algorithm requires a separate iterative technique (not provided) to calculate the force current for a given target time to failure. This document does not specify what test structure to use with this procedure. However, users of this algorithm report its effectiveness on both straight-lines and via-terminated test structures. Some test-structures design features are provided in JESD87 and in ASTM 1259M - 96.
Document identifier
JEDEC JEP119A
Title
A PROCEDURE FOR EXECUTING SWEAT
JEDEC Category
JC-14.2: Wafer-Level Reliability
Publication date
2003-08-01
International Relationship
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74 vnd |
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