This document describes an accelerated stress and test methodology for measuring device parameter changes of a single p-channel MOSFET after Negative Bias Temperature Instability (NBTI) stress at dc bias conditions. This document gives a procedure to investigate NBTI stress in a symmetric voltage condition with the channel inverted (VGS < 0) and no channel conduction (VDS = 0).There can be NBTI degradation during channel conduction (VGS < 0, VDS < 0), however, this document does not cover this phenomena.
Document identifier
JEDEC JESD90
Title
A PROCEDURE FOR MEASURING P-CHANNEL MOSFET NEGATIVE BIAS TEMPERATURE INSTABILITIES
JEDEC Category
JC-14.2: Wafer-Level Reliability
Publication date
2004-11-01
International Relationship
| Price |
60 vnd |
.jpg){kind=logo}
---Logo.jpg){kind=logo}
.jpg){kind=logo}
-_-logo.png){kind=logo}
.jpg){kind=logo}
.png)
