This standard defines ac test loads for dual-supply level translation devices. Uniform test loads enable easy comparison of electrical parameters of dual-supply level translation devices across functions, logic families and IC suppliers. This standard is only intended to apply to devices released subsequent to the publication of this document.
Document identifier
JEDEC JESD203
Title
STANDARD TEST LOADS FOR DUAL-SUPPLY LEVEL TRANSLATION DEVICES
JEDEC Category
JC-40.1: Digital Logic Families and Applications
Publication date
2005-11-01
International Relationship
| Price |
51 vnd |
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