This standard describes an algorithm for the execution of the isothermal test, using computer-controlled instrumentation. The primary use of this test is for the monitoring of microelectronic metallization lines at wafer level (1) in process development, to evaluate process options, (2) in manufacturing, to monitor metallization reliability and (3) to monitor/evaluate process equipment. While it is developed as a fast WLR test, it can also be an effective tool for complementing the reliability data obtained through the standard package level electromigration test.
Document identifier
JEDEC JESD61A.01
Title
ISOTHERMAL ELECTROMIGRATION TEST PROCEDURE
JEDEC Category
JC-14.2: Wafer-Level Reliability
Publication date
2007-10-01
International Relationship
| Price |
87 vnd |
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