This document defines a constant voltage stress test procedure for characterizing time-dependent dielectric breakdown or "wear-out" of thin gate dielectrics used in integrated circuit technologies. The test is designed to obtain voltage and temperature acceleration parameters required to estimate oxide life at use conditions. The test procedure includes sophisticated techniques to detect breakdown in ultra-thin films that typically exhibit large tunneling currents and soft or noisy breakdown characteristics. This document includes an annex that discusses test structure design, methods to determine the oxide electric field in ultra-thin films, statistical models, extrapolation models, and example failure-rate calculations.
Document identifier
JEDEC JESD92
Title
PROCEDURE FOR CHARACTERIZING TIME-DEPENDENT DIELECTRIC BREAKDOWN OF ULTRA-THIN GATE DIELECTRICS
JEDEC Category
JC-14.2: Wafer-Level Reliability
Publication date
2003-08-01
International Relationship
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74 vnd |
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