This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTV32852 24-bit to 48-bit SSTL_2 registered buffer for stacked DDR DIMM applications. The purpose is to provide a standard for the SSTV32852 logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.
Document identifier
JEDEC JESD82-6A
Title
DEFINITION OF THE SSTV32852 2.5 V 24-BIT TO 48-BIT SSTL_2 REGISTERED BUFFER FOR 1U STACKED DDR DIMM APPLICATIONS
JEDEC Category
JC-40: Digital Logic
Publication date
2004-11-01
International Relationship
| Price |
59 vnd |
.jpg){kind=logo}
---Logo.jpg){kind=logo}
.jpg){kind=logo}
-_-logo.png){kind=logo}
.jpg){kind=logo}
.png)
